1. Field of the Invention
The present invention relates generally to data clocking in an integrated circuit (IC).
2. Background Art
Power consumption of an integrated circuit (IC) can vary dramatically based on active functions on it. In order to minimize power consumption, functions are started and stopped as needed. This however leads to large changes in the load current. Large load steps, in turn, cause dynamic voltage variations in the supply voltage provided to the IC.
Much of the supply voltage variations are typically transient (e.g., less than 50 ns). In fact, the average supply voltage (over a 500 ns time window, for example) is fairly constant. In addition, worst-case voltage transients are extremely infrequent. Conventionally, however, the maximum clock frequency of the IC is selected based on the worst case voltage level. As such, although most of the time the voltage provided to the IC can support a higher clock frequency, the clock frequency is still constrained to accommodate the worst-case voltage transients.
Accordingly, there is a need for adaptive clock schemes that accommodate voltage transients.
The present invention will be described with reference to the accompanying drawings. Generally, the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.